In a digital PLL circuit which generates a clock signal of n/m times frequency from a reference clock signal, an infinite impulse response (IIR) or finite impulse response (FIR) digital filter is often used as a loop time constant. The digital filter is designed to determine a control voltage of a voltage control crystal oscillator (VCXO) from a phase error obtained by a phase comparator. Such a high-order filter requires a high-performance analog-to-digital converter and a digital signal processor (DSP) for arithmetic operations, increasing the size of a whole PLL circuit.
On the other hand, it is necessary to set a low cutoff frequency of a low-pass filter (to set a long control time constant) to realize ultra-high-stable phase synchronization in a digital PLL circuit. However, if a low cutoff frequency is set (a long control time constant is set), pull-in time becomes long, and a long-period fluctuation is caused by disturbance.
To solve the above problem, a cutoff frequency is made variable at the time of pulling-in and steady operation. Further, as disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2001-060864, an integrator circuit is used in a loop, and oscillation occurred in the steady operation caused by a time constant of the integrator circuit is prevented. However, in such a configuration, an analog-to-digital converter and DSP for arithmetic operations are required to realize a high-performance digital filter, and a circuit size is inevitably increased.
As described above, in a conventional digital PLL circuit, a control time constant must be set long to realize ultra-high-stable phase synchronization, and a long-period fluctuation is caused by disturbance. Besides, a digital filter increases a circuit size.